1. Field of the Invention
The present invention relates to integrated circuits, and more particularly, to scan testing of integrated circuits.
2. Background of Invention
Effective testing of integrated circuits significantly enhances the ability of integrated circuit developers and manufacturers to provide reliable devices. Various techniques have been employed to test integrated circuits during the manufacturing process. One such technique that is commonly known, and has been used within the industry for over twenty years is scan testing.
Scan testing provides an efficient approach to testing the structural integrity of devices, such as flip-flops, within a complex integrated circuit. Scan testing does not test integrated circuit-level functionality. Rather, test personnel use scan testing to confirm that individual flip-flops within an integrated circuit function properly. The sheer number of flip-flops within an integrated circuit, which is often greater than a million, presents a daunting challenge for testing. Scan testing addresses this challenge through the use of automated test units that provide test vectors to scan paths including thousands of flip-flops within integrated circuits that have been designed to support scan testing.
Typically, complex integrated circuits are designed and implemented as a series of interconnected functional blocks, each of which can be tested independently. Devices, such as flip-flops, within these functional blocks can be designed, such that they can be connected together in a scan path to support scan testing. Flip-flops and other elements within a scan path include, in addition to inputs and outputs used for normal operation, two inputs associated with the scan testing capability. These include a scan input (SI) and a scan enable (SE) input. Flip-flops within a scan path have their output connected to the SI input of a subsequent flip-flop. The first flip-flop within a scan path receives its input from an automated test unit through a test access port on the chip. The last flip-flop within a scan path provides its output to the automated test unit through a test access port. Many scan paths can exist within a single integrated circuit.
While scan testing provides significant benefits, challenges exist related to how to efficiently debug a scan testing failure to identify the source or sources of the failure. Identifying the source of a scan path failure can be quite difficult. A typical integrated circuit can include many scan paths with each scan path including as many as 10,000 flip-flops. Additionally, when doing scan testing tens of external clock sources can exist. These external clock sources are in turn coupled through multiplexers, logic gates and buffers to form complicated clock trees, such that a single scan path can be effected by multiple clock sources with thousands of clock tree elements.
A wide variety of sources for errors can exist. For example, errors can be caused by process, voltage, and/or temperature variations in which the circuit can function normally at a particularly frequency, temperature or voltage, but when these factors are changed errors can occur. In another example, an incorrect or faulty design, such as using a latch instead of a flip-flop, can cause errors. Yet another example, could be that the mask used to fabricate the integrated circuit was bad leading to broken connections between flip-flops or poorly performing flip-flops. In another case, a wrong wiring diagram can be used by the tester. In this case, a tester might perceive errors, which are not actually errors. Often times the errors are the result of failures in clock trees in which a clock signal is not properly propagated as a result of a bad multiplexer or buffer. Given the large number of scan paths, the large number of flip-flops in a scan path, the interrelationship between scan paths and the many possible sources of errors, debugging scan test failures can take days or even months.
When conducting scan testing, two types of general error results can occur. In the first case, the scan paths under test generates output signals, but the output does not match the expected results. For example, a scan path output may be expected to be 1 0 1 0 1 1 0 1 1 0, but the actual output is 0 0 0 1 1 0 1 1 0 1. These are abbreviated scan path outputs for ease of illustration. Actual outputs will consist of thousands of data points. In the second type of general error, a scan path under test generates no output signal. In this case, there are often multiple scan paths that have failed. This type of failure scenario is often the result of clock or clock tree problems.
Commonly owned, co-pending U.S. patent application Ser. No. 10/806,093, entitled “Methods for Debugging Scan Testing Failures of Integrated Circuits,” filed Mar. 23, 2004, provides methods for debugging scan testing failures of integrated circuits. U.S. patent application Ser. No. 10/806,093 (“'093 application”) is incorporated herein by reference in its entirety. The '093 application discloses a method that identifies the source of errors when scan paths are producing outputs that are incorrect. The methods dramatically reduce the time needed to debug circuit errors, thereby reducing integrated chip production costs and streamlining integrated circuit manufacturing. The method works well with the first type of errors discussed above. While the method can be used to debug errors in the second case, because the second case usually involves many failed scan paths, the method is not as effective and more efficient approaches are needed.
Commonly owned, co-pending U.S. patent application, entitled “Methods and Computer Program Products for Debugging Clock-Related Scan Testing Failures of Integrated Circuits,” (“Debugging Application,” application serial number to be determined) filed Sep. 28, 2004 by Amar Guettaf, provides methods for debugging scan testing failures of integrated circuits. The Debugging Application is incorporated herein by reference in its entirety. The Debugging Application discloses a method that identifies the source of errors when scan paths are producing no output. The methods dramatically reduce the time needed to debug circuit errors, thereby reducing integrated chip production costs and streamlining integrated circuit manufacturing. The method works well with the second type of errors discussed above. The combination of the methods provided in the '093 and Debugging applications can significantly reduce scan failure debugging times and increase manufacturing efficiency.
An additional challenge of scan testing is that external pins on an integrated circuit must be reserved to support scan testing. These external pins allow testers to connect integrated circuits to automatic testing tools, such as an Automatic Test Pattern Generation (ATPG) tool to support automated scan testing of an integrated circuit. Chip designers seek to minimize the number of external pins for testing to reduce design cost and allow a greater number of pins for actual use of the integrated circuit.
The number of internal clocks within an integrated chip impacts the number of external pins necessary for scan testing. In a typical chip design, there may be as many as 100 or more clock domains. A clock domain is a group of flip-flops and other logic that use the same clock. Multiple clock domains may impact one another through use of a common gate or flip-flop, providing further difficulties in testing. Independent clock domains are clock domains that are not impacted by each other in any way. The internal clocks that support clock domains often, but not always, have a different operating frequency. Thus, if each clock domain was to have a separate external pin to support testing the number of ports needed would be impractical.
Commonly owned, co-pending U.S. patent application Ser. No. 10/299,257, entitled “System and Method for Clock Domain Group Using Data Path Relationships,” filed Nov. 19, 2002 by A. Guettaf, provides methods for reducing the number of external ports needed for clock signals to support scan testing. U.S. patent application Ser. No. 10/299,257 (“'257 application”) is incorporated herein by reference in its entirety. The '257 application discloses a method to limit the number of scan test clocks and chip ports used for testing. The method includes identifying clock domains within a chip that are independent of each other (i.e., share no data path between elements within the clock domain) and grouping the independent clock domains together.
Further opportunities to improve the efficiency of scan testing by greater control of clock signals exist. In particular, methods to provide at-speed tests, while also limiting the number of external pins are needed. Conducting at-speed tests provides more robust test results in that the performance of a circuit may not be exactly the same when clock pulses at different speeds that the design speed are used. To reduce the number of pins clocks are used to drive a scan path at a speed different than the design speed with existing methods. Furthermore, in a static design external clock pins are established based on a certain circuit design. During development a circuit design may change resulting in external clock pins that may be used for clock domains that are no longer independent of one another.
What are needed are systems and method for controlling clock signals during scan testing integrated circuits that can support at-speed testing and be adjusted dynamically to address design changes, while minimizing the number of external pins needed to support scan testing clock inputs.